In U.S. Pat. No. 4,891,753 "Register Scoreboarding on a Microprocessor Chip" by David Budde, et al., granted on Jan. 2, 1990 and assigned to Intel Corporation, there is described apparatus for minimizing idle time when executing an instruction stream in a pipelined microprocessor by using a scoreboarding technique. A microinstruction is placed on a microinstruction bus and a microinstruction valid line is asserted. When a load microinstruction is decoded, a read operation is sent to a bus control logic, the destination register is marked as busy, and execution proceeds to the next current microinstruction. The marking provides an indication as to whether a current instruction can be executed without interfering with the completion of a previous instruction. The marking of registers gives rise to the term "scoreboarding". Execution of the current microinstruction proceeds provided that its source and destination registers are not marked "busy"; otherwise the microinstruction valid line is unasserted immediately after the current microinstruction appears on the microinstruction bus. The current microinstruction is thereby canceled must then be reissued. When data is returned as the result of a read operation, the destination registers are marked as "not busy".
It is an object of this invention to extend this prior scoreboarding technique to encompass all multiple cycle operations in addition to the load instruction.